(1) Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a non-volatile memory element, such as an EEPROM cell. Further, the present invention is concerned with a composite semiconductor memory device having a chip on which different-type memory cells, such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a DRAM (Dynamic Random Access Memory), are formed. Furthermore, the present invention is concerned with a method of producing such a "composite" semiconductor memory device.
(2) Description of the Prior Art
FIG. 1A is a cross-sectional view of a conventional EEPROM cell. The EEPROM cell shown in FIG. 1A includes a p-type semiconductor layer La, a gate insulating film Lb formed on the layer La, a floating gate Lf formed on the gate insulating film Lb, an insulating film Le covering the floating gate Lf, a control gate Lc formed on the insulating film Le and located above the floating gate Lf, and two n.sup.+ -type impurity diffused layers Ld formed in the semiconductor layer La and located on respective opposite sides of the control gate Lc. A bit line BL is connected to one of the two n.sup.+ -type diffused layers Ld, and a bulk line Vss is connected to the other n.sup.+ -type diffused layer Ld. The bit line BL and the bulk line Vss are connected to respective n.sup.+ -type diffused layers of other EEPROM cells. FIG. 1B shows a symbol i.e., schematic indication of the above EEPROM shown in FIG. 1A. The control gate Lc is connected to a word line WL.
A Fowler Nordheim write process (hereinafter simply referred to as an FN write process) is a known data writing process. In the FN write process, the two n.sup.+ -type diffused layers Ld are grounded and a high voltage of, for example, 15 V is applied to the control gate Lc. An electric field derived from the control gate Lc absorbs electrons in the semiconductor layer La, and electrons passing through the gate insulating film Lb are captured by the floating gate Lf. In this manner, data is written into the EEPROM cell.
According to the above FN write process, it is not necessary to apply a voltage to the n.sup.+ -type diffused layer Ld, and current does not flow in the bit line BL. Hence, it is possible to use a simple and low power consumption voltage control circuit used for writing data into the EEPROM cell.
However, it is impossible to apply the FN write process to a memory circuit in which a plurality of EEPROM cells are arranged in rows and columns, as shown in FIG. 2. In FIG. 2, the bulk line Vss and the bit line BL are set to a ground potential in order to select a first cell M11, and a voltage of 15 V is applied to a word line WL1. Simultaneously, a voltage of 15 V is applied to the control gate Lc of a second cell M21, and hence a charge flows into the floating gate Lf of the cell M21. Hence, data is written into not only the cell M11 but also the cell M21. That is, it is impossible to select only the cell M11.
With the above in mind, the following data write process has been used. A voltage of 12 V is applied to the word line WL1 connected to the first cell M11 which is to be selected, and the bulk line Vss is set to the ground potential. Further, a voltage of 6 V is applied to the bit line BL1. In this case, a hot carrier is generated in a channel formation area of the first cell M11. The hot carrier passes through the gate insulating film Lb, and flows into the floating gate Lf. In this manner, data is not written into the other cells M12, M21 and M22.
However, the above data writing process has a disadvantage in that a current flows in the bit line BL, and hence a large amount of energy is consumed. Further, the above-mentioned data writing process has a disadvantage in that data stored in other memory cells may be erased during the above data writing operation. That is, when the word line WL2 is set to the ground level, which switches the channel to the OFF state and which is equal to the substrate ground level, the voltage 6 V is applied to the bit line BL1, and when the bulk line Vss is set to the ground level in the state in which a charge is stored in the floating gate Lf of the cell M12 which is not currently selected, the charge in the floating gate Lf is absorbed in one of the two n.sup.+ -type diffused layers Ld, and the cell M12 switches to a data erased state.
It may be possible to reduce the voltage applied to the bit line BL in order to the above disadvantage. However, it becomes difficult to write data into the cell by a reduced bit-line voltage.
Conventionally, EEPROMs and DRAMs are formed on separate chips. However, as the feature scale is decreasing to a limit, it becomes more attractive to study how to increase the additional values of chips. For example, EEPROM cells and DRAM cells are formed on a single chip.
The EEPROM needs three wiring layers, that is, two polysilicon layers used for forming the floating gate Lf and the control gate Lc, and an aluminum layer used for forming the bit line BL. As shown in FIG. 3, the DRAM needs five wiring layers, that is, four polysilicon layers used for forming a gate electrode Li (formed on an insulating film Lh), a storage electrode Lk, a cell plate Ll and a bit line Lm, and an aluminum layer used for forming a wiring electrode Ln. A stacked capacitor Lj is composed of the storage electrode Lk, a dielectric film which is formed surround the storage electrode, and the cell plate L1. Since the number of wiring layers in the EEPROM is different from that in the DRAM, it is necessary to separately form the EEPROM cells and the DRAM cells on the single chip by respective different production processes. This increases the production cost and time. It should be particularly noted that the bit line BL, the storage electrode Lk and the cell plate Ll of the DRAM shown in FIG. 3 are not used in the EEPROM.